Electronic devices have been reduced in size and improved in functionality in recent years, and this has been accompanied by demand for size reduction and higher wiring density with regard to semiconductor chips as well. For example, with regard to a microprocessor designed according to the 90-nm rule, a clock frequency of several gigahertz and a driving current of 100 A have been attained, and further improvements in capability using conventional wiring techniques are approaching their limit. In order to realize a microprocessor in which the clock frequency exceeds 10 GHz and the driving current reaches several hundred amperes, a wiring technique of an entirely new structure is required. In particular, in the case of a semiconductor chip capable of high-speed operation, an increase in power distribution capability (wiring capacity) is sought as means for strengthening the power supply circuit serving as the source of power. On the other hand, in the case of high-speed signals, reducing parasitic capacitance produced between a signal pad and power supply circuit is important in terms of preventing a deterioration in signal characteristics. In order to improve supply of power and signal characteristics, there is need for a wafer-level re-wiring technique for fabrication on a semiconductor chip by a wiring technique different from that of the semiconductor chip.
An insulating material referred to as a “low-k material”, in which the specific inductivity is 2.5 or below, is now being employed in semiconductor devices. Further, lead-free solder materials are now being employed as the material of solder balls in view of effects upon the environment. However, a low-k material has a mechanical strength, such as hardness and elastic modulus, lower than that of silicon oxide, silicon nitride and silicon oxonitride, etc., which have been used heretofore as silicon-based elements. Further, in comparison with the conventional Pb—Sn eutectic solder material, a lead-free solder material has a poor creep characteristic. The creep characteristic indicates the ease of deformation of a material. Consequently, the amount of deformation of solder balls per se following the hardening thereof is small and residual stress within the solder balls is large.
Thus, in a semiconductor device using a low-k material and lead-free solder balls, residual stress within the solder balls produced at the time of packaging and thermal stress produced at the time of use can cause breakage at connections that include solder balls, or brittle fracture, exfoliation and cracking of the low-k material, which has a low mechanical strength, and it may be difficult to assure reliability when the package is assembled or put to practice use.
Conventionally, a semiconductor chip is mounted on a mounting substrate such as a printed board or built-up substrate and is used as a semiconductor device (package). An FCBGA (Flipchip Ball Grid Array) package or wafer-level CSP (Chip-Size Package) is known as such a semiconductor device. Various techniques are used to mitigate thermal stress in these packages.
The FCBGA is mainly used in applications that require stable supply of power supply voltage and support of high-speed signals. For example, Patent Document 1 discloses a technique for connecting a semiconductor chip to a BGA substrate using a solder bump and filling the device with an underfill resin in order to protect the small solder-bump connection. In accordance with Patent Document 1, it is possible to provide a highly reliable semiconductor device having a BGA structure in which severance at the solder bump and exfoliation of the semiconductor chip do not occur even if thermal stress is produced by thermal expansion.
Further, a wafer-level CSP formed to have a size substantially the same as that of a semiconductor chip is mainly used in small electronic devices such as mobile telephones and digital cameras. For example, Patent Document 2 discloses a technique for providing a layer having a low elastic modulus on a semiconductor chip and providing an external electrode terminal on this layer. In accordance with Patent Document 2, stress that acts upon metal balls can be mitigated by thus providing the layer having the low elastic modulus below the metal balls. Further, by providing the surface of the semiconductor chip with the metal balls spaced far away from the pads, stress produced in the metal balls can be prevented from propagating to the semiconductor chip connected to the pads.
Further, Patent Document 3 discloses a technique for directly providing a semiconductor element with a wiring layer for the purpose of furnishing a connection reliability greater than that of an FCBGA. In accordance with Patent Document 3, a resin substrate having a highly rigid core material is provided for an external terminal in a semiconductor device incorporating a semiconductor chip, thereby improving the long-term reliability of the package.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-A-11-74417
[Patent Document 2] Japanese Patent Kokai Publication No. JP-A-11-204560
[Patent Document 3] Japanese Patent Kokai Publication No. JP-P2002-246500A
[Patent Document 4] Japanese Patent Kokai Publication No. JP-A-10-51105
[Patent Document 5] Japanese Patent Kokai Publication No. JP-A-9-64493
[Patent Document 6] Japanese Patent Kokai Publication No. JP-A-6-334334